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For example, FIG. 1 shows an exemplary XCINV latch circuit 100. The XCINV latch circuit 100 includes first N-type metal-oxide semiconductor (NMOS) transistors N4 and N5 connected to receive an input voltage VIN. The input voltage VIN is biased to a predetermined value by coupling the input voltage VIN to the gate of a second NMOS transistor N6 via an inverter gate (IV_GATE) 121 and coupling a ground reference voltage VSS to the input voltage VIN. The gate of the second NMOS transistor N6 is biased to a predetermined value by coupling the input voltage VIN to the gate of the second NMOS transistor N6 via the inverter gate (IV_GATE) 121. A first NMOS transistor N2 and a second NMOS transistor N3 are coupled to a supply voltage VDD and are biased by the supply voltage VDD. A N-type metal-oxide semiconductor (NMOS) transistors N1 and N3 are coupled to receive an output voltage VOUT. An output voltage VOUT is generated by inverting the input voltage VIN and is coupled to the gate of the second NMOS transistor N3.
In the XCINV latch circuit 100 of FIG
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